The iQSPI_FlashMemory interface defines the contractual agreement for all QSPI flash memory controller implementations in the DadDrivers library. This abstract interface enables polymorphic programming, where specific classes (such as cW25Q128) can implement different flash technologies while sharing a unified API. The interface supports memory-mapped and indirect modes, as well as all fundamental operations: read, write, sector/block/chip erase, and hardware identification.
🎯 Enumerations and Associated Structures
FlashID
Element / Variable
Type / Value (if applicable)
Description
ManufactuerID
uint8_t
Manufacturer identification code (e.g., 0xEF for Winbond, 0xC2 for Macronix)
MemoryType
uint8_t
Flash memory type code (indicates capacity and generation)
Capacity
uint8_t
Memory capacity code (in MB: 16, 32, 64, 128, etc.)
Initializes the QSPI interface and flash memory. Configures the QSPI controller, performs a software reset, initializes status registers (block protection, driver strength), enables Quad I/O mode, and configures memory mapping. The default version implements reset and initialization of registers 1 and 3.
Parameter(s)
Â
phqspi
Pointer to the configured HAL QSPI handle (contains GPIOs for MOSI, MISO, CLK, CS)
DualMode
Flag enabling dual flash mode (two flash chips in parallel), default false
MemoryAddress
Base address for memory mapping in the processor’s address space, default 0x90000000
Return
HAL status code: HAL_OK success, HAL_ERROR initialization failure
ModeMemoryMap
Element
Details
Method
virtual HAL_StatusTypeDef ModeMemoryMap()
Description
Configures the flash memory in mapped mode, allowing the CPU to directly access the flash memory via standard read instructions (LDR/STR) without issuing SPI commands. The CPU can read the entire memory capacity as if it were RAM. Requires cache invalidation after activation.
Parameter(s)
None
Return
HAL status code: HAL_OK success, HAL_ERROR configuration failure
ModeIndirect
Element
Details
Method
virtual HAL_StatusTypeDef ModeIndirect()
Description
Restores indirect access mode after using memory mapping. The CPU returns to issuing standard SPI commands (READ, WRITE, ERASE) to access the flash memory. Required before any write or erase operations.
Parameter(s)
None
Return
HAL status code: HAL_OK success, HAL_ERROR configuration failure